דרושים וריפיקציה / ואלידציה

Senior Verification Engineers to Haifa

Education: Electrical Engineering/Computer science faculty

 8+ years of related work experience
 Experience in digital design verification.
 Hands-on experience in modern verification environments and tools:
1. Identifying test points and coverage points
2. Creating constraint random testbenches
3. Hardware Verification Languages and methodologies
1. Advantage to SystemVerilog
2. Advantage to OVM/UVM
4. Scripting languages
5. Assertions
6. Formal verification
 Understanding of HW SW partition and system level considerations.
 Ability to work in a team and to work in the Lab in order to assist in debugging the designs.

At least 5 years+ in VLSI verificationDeep experience with System-VerilogBSc in SW Engineering or Computer Science or ElectronicsExperience as team leader is an advantageOut of the box thinkerGood team work skillsTechnically motivated

לחברת הייטק באזור המרכז דרוש/ה Verification Engineer .

BSc in Computer science/ Computer engineering /Electrical engineering from known University- Must
At least 3 years experience with Specman / SystemVerilog based verification-Must.
In depth understanding of overall verification methodologies-Must.
Background in Networking IPs and SOC architecture-Must
Understanding of verification and design practices-Must

Design, implement and document verification blocks and coverage plans.
• Run and debug tests in complex verification environment (IP and SoC Level).
• Collect coverage and analyze regressions.
The position includes deep understanding of the architectural and micro architectural definitions and specifications

BSC בהנדסת אלקטרוניקה/ מדעי המחשב
2-5 שנות ניסיון בASIC VERIFICATION בעזרת SPECMAN
ניסיון בפיתוח בסביבת וריפיקציה בעזרת SPECMAN ו-VERILOG

Verification engineer that will take a major part in verification effort of first-generation wireless communications IC, Responsible for blocks and sub-chips verification environments , which includes environment architecture, testing plan definition, environment development and simulation.

B.Sc. in Computer/Electrical engineering
More than 7 years of experience in verification
Proven experience in entire verification flow: verification environment planning, environment coding, coverage and testing
Proven coding experience in SystemVerilog using VMM methodology or Specman (SystemVerilog experience – strong advantage)
Participate in verification infrastructure planning and coding
Scripting capabilities (Perl) - advantage

HW Architect to Haifa

Education: EE MsC required, PhD preferred
• At least 5 years of experience designing ASIC hardware or SOC architecture
o Familiar with digital design tools, including: RTL simulation, verification, synthesis, timing analysis, formal verification and lint
o Experience with Synopsys based flow
o Advantage
 Familiarity with Bus protocols (NoC, AXI, AHB)
 Knowledge of inter-chip standards like - eMMC, SD, SDIO, USB, PCIe, SATA, etc.
 Background in digital communications
 SystemC/TLM knowledge
• Ability to understand system wise aspects like interaction with software and firmware
• Ability to create digital micro architecture from specifications
• Good team player with ability to work as an individual contributor

The candidate will join the Qualcomm VLSI digital design team in Haifa. The team designs, validates and integrates RTL cores into Qualcomm chips across all tiers. Qualcomm uses tools and methodologies that are state-of-the-art in the area of VLSI. The design need to meet stringent functional area, timing and power requirements, and is implemented into the most advanced Silicon fabrication process in the industry. The candidate will join a team that handles the design from creating a micro-architecture spec through implementation and also into bringing the chip up in the lab and validating it.

Education: Electrical Engineering faculty

Requirements:

• 3+ years of related work experience.
• Knowledge in digital design techniques, preferably from the field of ASIC design front end activities.
• Ability to work in a team.
• Ability to understand system wise aspects like interaction of HW with SW and FW.
• Ability to create digital micro architecture from specifications.
• Familiar with the following is a plus:
• Digital design tools for the following flows: simulation, verification, synthesis, timing analysis, formal verification and lint.
• Background in digital communications and bus protocols and host interfaces a plus (AHB, USB, SDIO)

Design and Verification Engineers (graduated) to Haifa

Required
• Good school, good GPA (84+)
• 0-3 years of related work experience
• Knowledge in digital design techniques, preferably from the field of ASIC design front end activities
• Ability to work in a team.
• Ability to understand system wise aspects like interaction with software and lower level system components
A plus
• Past experience with relevant tools, especially with Verification OOP (or just OOP programming) tools like Vera or Specman
• Ability to create digital micro architecture from specifications – a plus
• Familiar with
• Familiar with digital design tools for the following flows: simulation, verification, synthesis, timing analysis, formal verification and lint. Familiarity with Synopsis based flow a plus
• Background in digital communications a plus
• Familiarity with bus protocols and host interfaces a plus (AHB, USB, SDIO)