דרושים מהנדס / הנדסאי ASIC

למטריקס צפון דרוש/ה מהנדס /ת חומרה ניסיון ב ASIC
אזור:תפן - כרמיאל

•Education: BSc. in either Electrical Engineering or Computer Sciences.
•2- 5 years of experience in ASIC verification using Specman.
•Experience in developing verification environments, using Specman and Verilog.
•Experience in coverage driven methodology.
•Good technical specification writing skills.
•Good verbal (English & Hebrew) and inter personal communication skills.

- B.Sc in Electrical Engineering from TAU, Teknion or Beer-Shiva (81, 8200).- Good graduate (above 82).- Preferred skills :- Experience 1-3 years (Required)- Verilog Language (Required).- Experience with ASICs or FPGAs (Required)- Experience in Altera

"Back-End engineer with experience in Digital implementation (Floor planning, Place and Rout=P&R) and Sign Off (STA - Static Taming analysis, Power analysis and IR drop analysis)."Experience in the Synthesis, Formal verification and DFT is a plus.

Frontend Engineer with experience in Synthesis and Formal verification.Experience in the DFT (Design for the test) or/and STA (static timing analysis) or/ and ATPG definitely a plus.Experience in digital implementation flow - a plus.Degree in Electrical E

At least 5 years experience in logic design, ASIC design preferred.At least 2 years experience in chip architecture.Proficiency in software design in an advantage.Areas of expertise: multicore, networking L4-L7.Parallel Computing CPU, NPU, DSP, MultiCore

B.Sc in Electrical Engineering / Computer Engineering Proven experience in automated verification tools (Specman)advantage :Experience in Software development using C/C++

At least five years experience in logic design, ASIC design preferred.

At least two years experience in chip architecture.

Proficiency in software design in an advantage.

Areas of expertise: multicore, networking L4-L7.

Qualifications
BS.EE (Grades average of 80 and above) from an accredited university.
Requirements
3+ years of VLSI verification experience.
Hands-on experience in modern Verification Environments and tools (System-Verilog/VERA/Specman).

Physical Designer Backend

Electrical science graduate for SOC Design physical implementation, physical verification and timing analysis, SOC design automation
Build a design, analyze and achieve performance goals, based on the require specifications
From Synthesis through P&R and static timing environment build and verification as well as physical DRC/LVS verification concluded by approved tapeout quality layout.
Tools & Programming skills in:
• Magma (Talus) synthesis & P&R
• Static timing analysis- Synopsis (PrimeTime)
• LVS/DRC – Caliber
• TCL programming

Design, implement and document verification blocks and coverage plans.
• Run and debug tests in complex verification environment (IP and SoC Level).
• Collect coverage and analyze regressions.
The position includes deep understanding of the architectural and micro architectural definitions and specifications

BSC בהנדסת אלקטרוניקה/ מדעי המחשב
2-5 שנות ניסיון בASIC VERIFICATION בעזרת SPECMAN
ניסיון בפיתוח בסביבת וריפיקציה בעזרת SPECMAN ו-VERILOG

מומחה/ית Timing לתפקיד Chip Design מאתגר, בחברת פיתוח בינלאומית מובילה.

בין 4-6 שנות ניסיון בביצוע Design, סינתזות, וTiming analysis
מומחה/ית ב Clock Design ו SDC
מומחה/ית ב SI Timing Analysis
ניסיון/ידע ב Place and Route- יתרון

HW Architect to Haifa

Education: EE MsC required, PhD preferred
• At least 5 years of experience designing ASIC hardware or SOC architecture
o Familiar with digital design tools, including: RTL simulation, verification, synthesis, timing analysis, formal verification and lint
o Experience with Synopsys based flow
o Advantage
 Familiarity with Bus protocols (NoC, AXI, AHB)
 Knowledge of inter-chip standards like - eMMC, SD, SDIO, USB, PCIe, SATA, etc.
 Background in digital communications
 SystemC/TLM knowledge
• Ability to understand system wise aspects like interaction with software and firmware
• Ability to create digital micro architecture from specifications
• Good team player with ability to work as an individual contributor

The candidate will join the Qualcomm VLSI digital design team in Haifa. The team designs, validates and integrates RTL cores into Qualcomm chips across all tiers. Qualcomm uses tools and methodologies that are state-of-the-art in the area of VLSI. The design need to meet stringent functional area, timing and power requirements, and is implemented into the most advanced Silicon fabrication process in the industry. The candidate will join a team that handles the design from creating a micro-architecture spec through implementation and also into bringing the chip up in the lab and validating it.

Education: Electrical Engineering faculty

Requirements:

• 3+ years of related work experience.
• Knowledge in digital design techniques, preferably from the field of ASIC design front end activities.
• Ability to work in a team.
• Ability to understand system wise aspects like interaction of HW with SW and FW.
• Ability to create digital micro architecture from specifications.
• Familiar with the following is a plus:
• Digital design tools for the following flows: simulation, verification, synthesis, timing analysis, formal verification and lint.
• Background in digital communications and bus protocols and host interfaces a plus (AHB, USB, SDIO)