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Verification Engineer

1-2 שנים |
משרה מלאה
| 26/01/2021
תיאור משרה

Be part of a dynamic and motivated verification team, taking part in developing from scratch a state-of-the-art Satellite SoC through the full life cycle: from design to production. The chip includes complex digital and analog modules such as high-speed signal processing, communication sub-system, computation sub system and more.
Responsible for various complex and innovative block(s) level and SoC verification using state of the art verification technologies.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
"Define and develop verification test plans, test benches, protocol monitors, and high-coverage stimulus vectors.
Active role defining and implementing advanced verification flows and techniques.
משרה 101970

דרישות התפקיד

"At least 3 years of hands on verification experience (block level and/or SoC) with SystemVerilog, UVM and/or Specman.
"Hands on with design flows and methodologies used for advanced verification.
"Understanding of overall verification methodologies.
"Background in networking IPs and SoC architecture.
"Understanding of verification and design practices.
"Scripting and programming experience using several of the following: Perl, Python, Verilog, System Verilog, UVM, DPI and C/C++.
"Clear sense of urgency and a "can do" attitude. Effective teamwork and collaboration skills.
"Self-learning capabilities, adapt to changes and study new technical fields.
Education: B.Sc/M.Sc in Electrical or Computer Engineering or Computer Science.