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VLSI Verification Senior Engineer

1-2 שנים |
משרה מלאה
| 27/04/2021
תיאור משרה

For a hi-tech company developing products for wireless networks in the home, with offices in the Sharon we are looking fot a VLSI Verification Senior Engineer
In this role you will be responsible for taking part in SoC verification process of next generation WiFi chip in fast growing startup company.
You will define verification test plan for sub-system verification environment, define coverage metrics, design and implement verification environment including integration of existing verification IPs.
Option to act as a Technical leader
משרה 41429

דרישות התפקיד

"Above 5 years experience in UVM, VMM or E (Specman) - mandatory (At least 1 year with UVM)
"BSc / MSc. in Electronics Engineering from a known university
"Experience in development of Sub-System Verification Environments involving different IPs
"Substantial experience with verification methodologies (Reusable/Random Based/Coverage Driven)
"Very good debugging skills
"Good Verilog skills
"Good C skills is an advantage
"Highly motivated person. Ability to get into a complex Verification Environment and own it
"Quick learner
"Knowledge with OFDM MAC/PHY is a big advantage
"Very good human relations