Verification engineer

תל אביב |
1-2 שנים |
משרה מלאה
| 06/05/2021
תיאור משרה

A great startup company in the AI world is looking for Verification Engineer !

We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in big data computing! If you enjoy working on cutting edge technologies, solving complex problems, have a team spirit and a can-do-attitude – Your place is with us!
What you’ll be doing:

Design, review and deploy UVM-based verification environments in block, chip, and system levels.
Verify the design and hunt for bugs, working closely with other teams.
Build sophisticated, automated & randomized environments to cover all corners of the design.
Use state of the art verification tools and technologies.
Enhance the verification cycle-time by building automation infrastructure.

דרישות התפקיד

BSC EE-engineer/Computer-science, GPA 85 or above
1-3 years of hands-on chip verification experience
Scripting knowledge: Python/TCL/Perl
A team player, quick learner, good multitask ability, self-managed.

Knowledge with UVM
Experience with RTL design, SystemVerilog
Knowledge with industry protocols such as AXI, Pcie, DDR