Verification Engineer

מספר מקומות |
1-2 שנים |
משרה מלאה ועוד
| 12/09/2021
תיאור משרה

Develop verification concept and methodologies for standalone IP's and full Networking system

דרישות התפקיד

University graduate with 0-15 years' experience in the industry
2 years' experience in Verification
Experience with UVM, system Verilog or E (Specman) is a big advantage.
Familiar with verification methods
Knowledge with UVM, system Verilog or E (Specman) - an advantage

טווח שכר