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Position Overview
The Senior FPGA Team Lead owns the architecture, design, and implementation of complex FPGA-based systems, with deep expertise in signal processing and high-speed digital interfaces. This person provides technical leadership and mentorship to a multidisciplinary team of FPGA engineers, driving system-level design decisions in close collaboration with system, RF, hardware, and software teams. The role owns the full development lifecycle — from requirements through design, simulation, implementation, and validation — and leads lab bring-up, debugging, and performance optimization, while defining best practices, coding standards, and design methodologies for the team.
Key Responsibilities:
Lead architecture, design, and implementation of complex FPGA-based systems.
Provide technical leadership and mentorship to FPGA engineers.
Drive system-level design decisions in collaboration with system, RF, hardware, and software teams.
Design and implement advanced DSP algorithms, including filtering and channelization.
Develop and integrate high-speed data paths and interfaces, ensuring signal integrity and robust operation of high-speed links.
Optimize designs for performance, latency, and resource utilization.
Own the full development lifecycle: requirements, design, simulation, implementation, and validation.
Lead lab bring-up, debugging, and performance optimization.
Define best practices, coding standards, and design methodologies.
Qualifications .
דרישות התפקיד
Education:
B.Sc. or M.Sc. in Electrical Engineering or a related field.
Experience:
8+ years of FPGA design experience, with strong hands-on experience in FPGA design and development, deep expertise in digital signal processing (DSP), and high proficiency in VHDL, Verilog, and SystemVerilog. Strong system-level understanding and integration experience is required, along with a deep understanding of SERDES, transceivers, and clocking architectures, and proven experience with high-speed link bring-up and lab debugging. Fluent English (spoken and written) is required.
Preferred Qualifications:
Experience with Xilinx/AMD FPGA devices and toolchains (Vivado, Vitis).
Experience with RF/wireless communication systems (LTE/5G).
Experience with RFSoC/Zynq platforms.
Proficiency with MATLAB or Python for algorithm development.
Experience with real-time, high-throughput systems.
Soft Skills:
Strong leadership and mentoring capabilities.
Ability to drive complex technical decisions independently.
Excellent analytical and problem-solving skills.
Strong communication and cross-functional collaboration skills.
Technology Stack:
VHDL, Verilog, and SystemVerilog for FPGA design and development.
Xilinx/AMD FPGA devices and toolchains, including Vivado and Vitis.
RFSoC and Zynq platform architectures.
High-speed SERDES, transceiver, and clocking design and test equipment.
MATLAB and Python for algorithm development and simulation.
Lab bring-up and debug equipment for high-speed digital interfaces (e.g., oscilloscopes, protocol analyzers).
Physical Requirements
Ability to lift up to 25 lbs.
Ability to use a computer for extended periods.
Ability to work in an office, lab, or a combination of both environments, including hands-on work with FPGA boards and high-speed test equipment.
Ability to work in lab environments involving extended standing and close-tolerance bench work during bring-up and debug.
Ability to travel occasionally to support lab bring-up, integration, or cross-site collaboration as needed.
This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demand
* משרה זו פונה לנשים וגברים כאחד.
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