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דרושים מהנדס רכיבים VLSI
Design and Verification Team Lead Engineer
לפני 7 שעותשלח קורות חייםהוסף לסל
MarvellMarvell is offering a great opportunity to join the Switch IP department and be part of our IP development for the next generation Switch. Our development teams work with architects to influence the unit architecture, plan micro-architecture and implement the design in Verilog or SV, plan and implement complex and advanced verification environments, define and execute the verification plan until quality criteria is met.
As a team leader in the IP department you’ll directly manages 2-6 engineers and their tasks. The team leader manages several units or a cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification, responsible for the full development flow and interface with external teams.
As a leader you will direct people to form a successful and motivated team and drive their career development. You will be responsible for team execution and tasks prioritization. You will share the activity of the team by direct execution of selected tasks (“hands-on”).
Our sites are located in Petach-Tikve and Yokneam.
As a team leader in the IP department you’ll directly manages 2-6 engineers and their tasks. The team leader manages several units or a cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification, responsible for the full development flow and interface with external teams.
As a leader you will direct people to form a successful and motivated team and drive their career development. You will be responsible for team execution and tasks prioritization. You will share the activity of the team by direct execution of selected tasks (“hands-on”).
Our sites are located in Petach-Tikve and Yokneam.
Job Requirements:• 8+ years’ experience in VLSI development
• Hands-on experience in design and verification
• Team management experience
• Excellent personal skills
• Visionary and strategic
• High motivation and desire to influence
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-engineer_171438
• Hands-on experience in design and verification
• Team management experience
• Excellent personal skills
• Visionary and strategic
• High motivation and desire to influence
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-engineer_171438
Required Experience:7 שנים ומעלה
Locations:מרכז, שרון, יהודה ושומרון
Location:פ"ת
Sub Categories:חומרה - ניהול, מהנדס רכיבים VLSI, ראש צוות חומרה
Job Scopes:משרה מלאה
For more jobs and additional info about:Marvell
Architectural Exploration and Modeling student
לפני 7 שעותשלח קורות חייםהוסף לסל
MarvellThe requisition is for an intern position in the switching architecture group
• We are developing innovative architectures that require deep architecture exploration.
• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.
The activity is partitioned to two stages:
• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.
• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.
The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.
In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.
• We are developing innovative architectures that require deep architecture exploration.
• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.
The activity is partitioned to two stages:
• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.
• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.
The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.
In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.
Job Requirements:Education: 3rd year student for BSC in electrical or computer engineering
Skills:
• Programming – Advantage
o C/C++, SystemC, Perl, Python scripting
• Knowledge - Advantage
o Computer architecture
o Networking
Skills:
• Programming – Advantage
o C/C++, SystemC, Perl, Python scripting
• Knowledge - Advantage
o Computer architecture
o Networking
Required Experience:ללא נסיון
Locations:מרכז, שרון, שפלה, ירושלים
Location:פ"ת
Sub Categories:סטודנטים - חומרה, מהנדס רכיבים VLSI, מהנדס / הנדסאי ASIC
Job Scopes:משרה מלאה
For more jobs and additional info about:Marvell
Design and Verification Team Lead Engineer
לפני 10 שעותשלח קורות חייםהוסף לסל
MarvellMarvell is offering a great opportunity to join the Switch IP department and be part of our IP development for the next generation Switch. Our development teams work with architects to influence the unit architecture, plan micro-architecture and implement the design in Verilog or SV, plan and implement complex and advanced verification environments, define and execute the verification plan until quality criteria is met.
As a team leader in the IP department you’ll directly manages 2-6 engineers and their tasks. The team leader manages several units or a cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification, responsible for the full development flow and interface with external teams.
As a leader you will direct people to form a successful and motivated team and drive their career development. You will be responsible for team execution and tasks prioritization. You will share the activity of the team by direct execution of selected tasks (“hands-on”).
Our sites are located in Petach-Tikve and Yokneam.
As a team leader in the IP department you’ll directly manages 2-6 engineers and their tasks. The team leader manages several units or a cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification, responsible for the full development flow and interface with external teams.
As a leader you will direct people to form a successful and motivated team and drive their career development. You will be responsible for team execution and tasks prioritization. You will share the activity of the team by direct execution of selected tasks (“hands-on”).
Our sites are located in Petach-Tikve and Yokneam.
Job Requirements:• 8+ years’ experience in VLSI development
• Hands-on experience in design and verification
• Team management experience
• Excellent personal skills
• Visionary and strategic
• High motivation and desire to influence
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-engineer_171438
• Hands-on experience in design and verification
• Team management experience
• Excellent personal skills
• Visionary and strategic
• High motivation and desire to influence
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-engineer_171438
Required Experience:7 שנים ומעלה
Locations:מרכז, שרון, שפלה, יהודה ושומרון
Location:פ"ת
Sub Categories:חומרה - ניהול, מהנדס רכיבים VLSI, ראש צוות חומרה
Job Scopes:משרה מלאה
For more jobs and additional info about:Marvell
Design and Verification Engineer
לפני 10 שעותשלח קורות חייםהוסף לסל
MarvellCome join Marvell, our excellent team working on cutting-edge Intelligent Processors.
Drive the future of data processing for the Enterprise, Data Center, and Wireless Infrastructure applications.
Take the next step in your career. Learn and share your knowledge and expertise with others.
Feel excited to work with great colleagues, in a dynamic environment.
Invent, define, and implement.
As a Design and Verification Engineer, you will participate in all front-end phases of product development.
You will participate in Design (Definition, u-Architecture, RTL design and Debug) and/or Verification activities (UVM TB planning and coding, random testing and debugging)
Drive the future of data processing for the Enterprise, Data Center, and Wireless Infrastructure applications.
Take the next step in your career. Learn and share your knowledge and expertise with others.
Feel excited to work with great colleagues, in a dynamic environment.
Invent, define, and implement.
As a Design and Verification Engineer, you will participate in all front-end phases of product development.
You will participate in Design (Definition, u-Architecture, RTL design and Debug) and/or Verification activities (UVM TB planning and coding, random testing and debugging)
Job Requirements:• B.Sc. or above in Electronic Engineering or equivalent
• At least 3 years of experience in RTL design or verification
• Design RTL experience in Verilog/SV or verification experience in SV-UVM / e-UVM
• Good team work and collaboration skills
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-Engineer_190666
• At least 3 years of experience in RTL design or verification
• Design RTL experience in Verilog/SV or verification experience in SV-UVM / e-UVM
• Good team work and collaboration skills
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-Engineer_190666
Required Experience:3-4 שנים
Locations:מרכז, שרון, צפון, יהודה ושומרון
Location: More than one
Sub Categories:וריפיקציה / ואלידציה, מהנדס רכיבים VLSI, מהנדס אלקטרוניקה
Job Scopes:משרה מלאה
For more jobs and additional info about:Marvell
Design and Verification Engineer
לפני 10 שעותשלח קורות חייםהוסף לסל
MarvellCome join Marvell, our excellent team working on cutting-edge Intelligent Processors.
Drive the future of data processing for the Enterprise, Data Center, and Wireless Infrastructure applications.
Take the next step in your career. Learn and share your knowledge and expertise with others.
Feel excited to work with great colleagues, in a dynamic environment.
Invent, define, and implement.
As a Design and Verification Engineer, you will participate in all front-end phases of product development.
You will participate in Design (Definition, u-Architecture, RTL design and Debug) and/or Verification activities (UVM TB planning and coding, random testing and debugging)
Drive the future of data processing for the Enterprise, Data Center, and Wireless Infrastructure applications.
Take the next step in your career. Learn and share your knowledge and expertise with others.
Feel excited to work with great colleagues, in a dynamic environment.
Invent, define, and implement.
As a Design and Verification Engineer, you will participate in all front-end phases of product development.
You will participate in Design (Definition, u-Architecture, RTL design and Debug) and/or Verification activities (UVM TB planning and coding, random testing and debugging)
Job Requirements:• B.Sc. or above in Electronic Engineering or equivalent
• At least 3 years of experience in RTL design or verification
• Design RTL experience in Verilog/SV or verification experience in SV-UVM / e-UVM
• Good team work and collaboration skills
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-Engineer_190666
• At least 3 years of experience in RTL design or verification
• Design RTL experience in Verilog/SV or verification experience in SV-UVM / e-UVM
• Good team work and collaboration skills
Website: https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Petach-Tikva/Design-and-Verification-Engineer_190666
Required Experience:3-4 שנים
Locations:מרכז, שרון, צפון, יהודה ושומרון
Location: More than one
Sub Categories:וריפיקציה / ואלידציה, מהנדס רכיבים VLSI, מהנדס אלקטרוניקה
Job Scopes:משרה מלאה
For more jobs and additional info about:Marvell
Senior VLSI Design Verification Engineer
10/12/2019שלח קורות חייםהוסף לסל
High Tech CompanyFor an established hi-tech company developing products for the mobile-device market, with offices in the Haifa area
To join our company of inventors that is unlocking 5G, ushering in the age of rapid acceleration in connectivity, and creating new possibilities that will transform industries, generate jobs and enrich lives משרה 99573
To join our company of inventors that is unlocking 5G, ushering in the age of rapid acceleration in connectivity, and creating new possibilities that will transform industries, generate jobs and enrich lives משרה 99573
Job Requirements:B.Sc. in Computer Science / Electrical Engineering
At least 5 years experience as a Design Verification Engineer - a must
In-depth understanding of OOP / SystemVerilog / UVM - a must
Experience with scripting languages (Python / Perl) - a must
Experience debugging from RTL to system level - a must
Team player with good communication skills - a must
At least 5 years experience as a Design Verification Engineer - a must
In-depth understanding of OOP / SystemVerilog / UVM - a must
Experience with scripting languages (Python / Perl) - a must
Experience debugging from RTL to system level - a must
Team player with good communication skills - a must
Required Experience:7 שנים ומעלה
Locations:שרון, צפון
Location: More than one
Sub Categories:וריפיקציה / ואלידציה, מהנדס רכיבים VLSI, מהנדס / הנדסאי ASIC
Job Scopes:משרה מלאה
Senior VLSI PHY Design Engineer
10/12/2019שלח קורות חייםהוסף לסל
High Tech CompanyFor an established hi-tech company developing products for the mobile-device market, with offices in the Haifa area
To join us in the development of new Wi-Fi and automotive SoC products משרה 99566
To join us in the development of new Wi-Fi and automotive SoC products משרה 99566
Job Requirements:B.Sc. in Computer Science / Electrical Engineering from an accredited university - a must
At least 5 years experience as VLSI front-end engineer - a must
Experience with Verilog design coding - a must
Experience in micro-architecture and the design of complex Digital Signal Processing blocks - a must
At least 5 years experience as VLSI front-end engineer - a must
Experience with Verilog design coding - a must
Experience in micro-architecture and the design of complex Digital Signal Processing blocks - a must
Required Experience:7 שנים ומעלה
Locations:שרון, צפון
Location: More than one
Sub Categories:מהנדס / הנדסאי ASIC, מהנדס רכיבים VLSI
Job Scopes:משרה מלאה
Verification Engineer Team leader- Petach Tikva
10/12/2019שלח קורות חייםהוסף לסל
Veriest SolutionsVeriest solutions is seeking for an experienced Verification engineer to lead a team for several new and unique projects
Our offices are located in Petach Tikva
Our offices are located in Petach Tikva
Job Requirements:- 5+ years of verification experience.
- System Verilog “hands-on” experience – must
- B.Sc in electronics / computer engineering / computer science
- Creative and Service provider abilities
- Fast learning areas and issues
- System Verilog “hands-on” experience – must
- B.Sc in electronics / computer engineering / computer science
- Creative and Service provider abilities
- Fast learning areas and issues
Required Experience:5-6 שנים
Locations:מרכז, שרון
Location:פ"ת
Sub Categories:מהנדס רכיבים VLSI, וריפיקציה / ואלידציה, ראש צוות חומרה
Job Scopes:משרה מלאה, משרה חלקית, משרה זמנית, משמרות
For more jobs and additional info about:Veriest Solutions
FPGA designer- Petach Tikva
10/12/2019שלח קורות חייםהוסף לסל
Veriest SolutionsExperienced FPGA Engineer, with strong capabilities throughout the entire FPGA development process to be part of an FPGA Design team in challenging high speed FPGA design activities
• Design, as part of the team, complex blocks in the FPGA, integration of IP blocks, DSP functions
Work According to best practices/design processes to support high quality designs
Our offices are located in Petach Tikva
• Design, as part of the team, complex blocks in the FPGA, integration of IP blocks, DSP functions
Work According to best practices/design processes to support high quality designs
Our offices are located in Petach Tikva
Job Requirements:• B.Sc. in Electrical Engineering
• Experience with Xilinx (or Altera) flows, including RTL Coding, synthesis, place & route, timing constraints and closure
• Experienced with DSP Implementations (Filters Design, NCO Design, DDC, DUC & Multi-rate design)
• Experienced with architecture, specs, documentation.
• Experienced with VHDL/Verilog coding and debugging.
• Experienced with lab FPGA debug tools (like Chipscope / Signaltap).
• Knowledge in FPGA design - SoC, HW/SW implementations, memory interfaces, IP blocks integration
• At least 3 years proven experience in FPGA digital design.
• Proven experience with complex SoC architectures.
• Experience with Xilinx (or Altera) flows, including RTL Coding, synthesis, place & route, timing constraints and closure
• Experienced with DSP Implementations (Filters Design, NCO Design, DDC, DUC & Multi-rate design)
• Experienced with architecture, specs, documentation.
• Experienced with VHDL/Verilog coding and debugging.
• Experienced with lab FPGA debug tools (like Chipscope / Signaltap).
• Knowledge in FPGA design - SoC, HW/SW implementations, memory interfaces, IP blocks integration
• At least 3 years proven experience in FPGA digital design.
• Proven experience with complex SoC architectures.
Required Experience:3-4 שנים
Locations:מרכז, שרון
Location:פ"ת
Sub Categories:מהנדס / הנדסאי FPGA, מהנדס רכיבים VLSI
Job Scopes:משרה מלאה
For more jobs and additional info about:Veriest Solutions
Experienced Verification Engineer
09/12/2019שלח קורות חייםהוסף לסל
Experis TA1A global tech company located in Tel-Aviv is looking for an Experienced Verification Engineer.
Verification Engineer responsible for various platform team as part of emerging VLSI group.
Responsible for Various IPs (PHY, Networking IPs etc) and SOC Verification.
Taking part in IP definition and implementation.
Defining Test plans, coverage plans etc.
Working closely with system team ensuring correct implementation of the products requirements.
Verification Engineer responsible for various platform team as part of emerging VLSI group.
Responsible for Various IPs (PHY, Networking IPs etc) and SOC Verification.
Taking part in IP definition and implementation.
Defining Test plans, coverage plans etc.
Working closely with system team ensuring correct implementation of the products requirements.
Job Requirements:1-3 years of experience - MUST.
Leading university degree.
In depth understanding of overall verification methodologies.
Background in Networking IPs and SOC architecture.
Understanding of verification and design practices.
Experience with SPECMAN - Advantage.
Experience with C coding - Advantage.
Verilog - Advantage.
Dynamic person.
Leading university degree.
In depth understanding of overall verification methodologies.
Background in Networking IPs and SOC architecture.
Understanding of verification and design practices.
Experience with SPECMAN - Advantage.
Experience with C coding - Advantage.
Verilog - Advantage.
Dynamic person.
Required Experience:3-4 שנים
Locations:מרכז, שפלה
Location:תל אביב יפו
Sub Categories:וריפיקציה / ואלידציה, מהנדס אלקטרוניקה, מהנדס רכיבים VLSI
Job Scopes:משרה מלאה
For more jobs and additional info about:Experis TA1
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