לצערנו המשרה כבר לא בתוקף

Analog Modeling Verification Engineer

5-6 שנים |
משרה מלאה
| 16/04/2024
תיאור משרה

- Develop analog modeling verification strategies for complex electronic systems.
- Create and maintain Behavioral Models (BM) for Analog designs to enable digital verification.
- Utilize mixed-signal dynamic verification techniques using chip digital design tools.
- Design and execute SystemVerilog testbenches for analog modeling verification.
- Analyze verification results and collaborate with analog design teams to resolve discrepancies.
- Stay updated with advancements in analog modeling verification methodologies and tools.
- Contribute to improving verification processes within the organization.

דרישות התפקיד

- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 5 years of experience in analog modeling verification.
- Proficiency in SystemVerilog, UVM methodologies, and Virtuoso Schematics tools.
- Basic understanding of analog design principles.
- Experience with both Synopsys and Cadence tools is preferred.
- Strong communication and problem-solving skills.

* משרה זו פונה לנשים וגברים כאחד.