Senior Verification Engineer

מספר מקומות |
5-6 שנים |
משרה מלאה
| 19/04/2026
תיאור משרה

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.
;Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

דרישות התפקיד

• 5+ years of experience as a Verification Engineer.
• B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
• Strong knowledge of System Verilog and UVM methodology.
• Experience in pre-silicon functional unit level/cluster/full chip verification.
• Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
• Familiarity with SoC architecture, CPU subsystems, and multi-core designs.
Advantages
• Knowledge of formal verification and emulation/FPGA prototyping.
• Exposure to AI/Networking workloads and performance validation.

* משרה זו פונה לנשים וגברים כאחד.