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About the job:
Do you want to be part of Google’s next generation of data centers? Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. As part of our new server chip design center, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you'll contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality RTL. Additionally, you will solve technical problems with innovative micro-architecture and practical logic solutions, while evaluating design options with complexity, performance, power and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Define architecture/microarchitecture specifications and work closely with others to ensure end to end solutions.
Take ownership of one or more sub modules and RTL implementation and participate in post silicon systems bring-up and debug.
Converge functionality and PPA of the design.
Contribute to design methodology, libraries and code review.
Define chip level features and solutions and drive implementation.
Bachelor’s degree in Electrical Engineering, or equivalent practical experience.
Experience with 2 or more SoC cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power design.
Experience in high performance high frequency, low power designs.
Master’s degree in Electrical Engineering.
Experience in VLSI design in SoC or experience with multiple-cycles of SoC in ASIC design.
Verilog experience and experience with scripting and programming with Perl, C, C++, and TCL.
Experience in several successful ASIC products from concept to silicon and knowledge of machine learning.
Vertical expertise in micro-processor/accelerator ASIC from feature definition to tape-out.
Deep understanding in computer architecture/memory subsystem architecture.