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A global high tech company in the field of satellite communication is looking for a Verification Engineer
Define and track detailed test plans for the different modules and top levels.
Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
Keep track of coverage metrics and bugs encountered and fixed.
Implement self-testing directed and random tests.
Ability to communicate clearly.
3 years experience of System Verilog OVM/UVM DV experience
BSc/ MSc in Electrical Engineering
Knowledge of Python, Perl, shell scripting
Knowledge with assertions (SVA) or others
Knowledge of digital FPGAs design flows
Familiar with Matlab language
Familiar with Linux
Familiar VCS and Synopsis