Senior RTL designer/micro-architect

3 years of experience as Silicon/FPGA/ASIC designer/micro-architect
• Extensive experience with Verilog/System-Verilog.
• Familairity with simulation tools/environments.
• Strong team player eager to learn and share, think fast, act fast
• Entrepreneurial can-do attitude, open-mind behavior
• Self-motivated, able to work with minimal guidance and supervision
Advantage – background in one or more of the following domains:
• ARM/x86/GPU architectures
• Virtualization/Containers and OS-related mechanisms
• Storage elements, block devices, NVMe
• PCIe (Gen3 and above)
• Memory Controllers, Caches, HBM, (LP)DDR5/4
• Ethernet (100G/200G and above)
• Xilinx/Intel FPGAs